This invention relates generally to analog-to-digital (A/D) converters, and more particularly, the invention relates to semi-flash A/D converters.
In converting an analog signal to an N-bit digital signal, a full flash converter requires 2.sup.N -1 comparators. For example, an 8-bit digital signal requires 255 comparators for full flash conversion. The 255 comparators are tied to a 256 resistor ladder which provides the voltage reference corresponding to the 256 voltage levels represented by the 8-bit digital signal.
A two-step or semi-flash A/D converter can reduce the number of comparators required for an 8-bit digital signal from 255 to 31. In obtaining the 8-bit signal, two 4-bit flash conversions are made in sequence; first the four most significant bits are obtained and then the four least significant bits are obtained. After the most significant (M/S) 4-bit conversion, the four bits are converted to analog form and subtracted from the input signal, V.sub.IN. The remainder is then applied to a second 4-bit converter to get the least significant (L/S) bits. The four M/S bits are then combined with the four L/S bits as the 8-bit digital number.
The advantage of the semi-flash conversion is the reduction in hardware as compared to a full-flash converter. The architecture can be further simplified by reusing the M/S flash converter to do the L/S flash conversion. This is possible since the M/S flash and the L/S flash occur at different times. The output of the M/S conversion could be latched while the L/S conversion is performed, thus providing a continuous D/A output. However, while the concept of reusing the M/S converter for the L/S conversion is conceptually simple, from a hardware point of view the concept is impractical using conventional A/D converters and comparators.